Professor Sotirios G. Ziavras
ECE Department
New Jersey Institute of Technology
USA
E-mail: ziavras@adm.njit.edu

Abstract:
Heterogeneous chip multiprocessors form powerful computing platforms. For high-performance or real-time applications, their design should also rely on acceptable energy budgets. The inclusion of reconfigurable hardware can enhance these platforms even further. This talk first presents a very versatile family of reconfigurable chip multiprocessors that can support the run-time reconfiguration of resources in efforts to match target applications for better performance and/or lower energy consumption. This talk then introduces another family of reconfigurable chip multiprocessors where the hardware can be customized to speed up the execution of time-consuming application kernels. Hardware reconfiguration can then facilitate various customized kernels as execution proceeds. This approach greatly reduces the space and energy requirements, attributes that appeal to high-performance embedded designs. The kernel execution should be prudently scheduled considering the reconfiguration overheads. Suitable task scheduling and resource reconfiguration policies are presented for these families of chip multiprocessors and benchmarks are enlisted as well to showcase their success.

Brief Biography of the Speaker:
Dr. Sotirios G. Ziavras received the Diploma in Electrical Engineering from the National Technical University of Athens, Greece, the M.Sc. in Computer Engineering from Ohio University, and the Ph.D. in Computer Science from George Washington University (GWU). He was a Distinguished Graduate Teaching Assistant and Research Assistant at GWU, and also received the Richard Merwin Ph.D. Fellowship. He was with the Center for Automation Research at the University of Maryland, College Park, from 1988 to 1989, focusing on supercomputing. He was a visiting Professor at George Mason University in Spring 1990. He joined in Fall 1990 the ECE Department at NJIT as an Assistant Professor. He is currently a Professor as well as the Director of the Computer Architecture and Parallel Processing Laboratory (CAPPL). He served as the Associate Chair for Graduate Studies for four years.
He received the National Science Foundation (NSF) Research Initiation Award in 1991. In 1996 he lead an NSF/DARPA/NASA-funded New Millennium Computing Point Design project for Petaflops computing. He has received research grants in excess of $2.5M. He has served as an Associate Editor of the Pattern Recognition journal and serves regularly as a member of Conference Program Committees. He is the author of about 140 scientific papers. He is listed, among others, in Who's Who in Science and Engineering, Who's Who in America, Who's Who in the World, and Who's Who in the East. His main research interests are reconfigurable and high-performance computing, computer architecture and embedded systems.