WSEAS Transactions on Circuits and Systems
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Print ISSN: 1109-2734
E-ISSN: 2224-266X
Volume 12, 2013
Issue 1, Volume 12, January 2013
Title of the Paper: Analysis of Regimes of Voltage Regulators with Limited Capacity Voltage Sources. Geometrical Approach
Authors: Penin Alexandr
Abstract: In power supply systems with limited capacity voltage sources, the limitation of load power is appeared. The systems with PWM boost converters may be the example of ones. But, the boost converters have a nonlinear and two-valued regulation characteristic too. Therefore, it is necessary to correctly determine the regime parameters of the converter relative to maximum permissible load voltage and control pulse width. If such power supply system contains also a quantity of loads with individual regulated voltage converters, then an interference of the converters takes place on the load regimes. Therefore, it is important to carry out the analysis of interference and to obtain relationships for definition of converter parameters. In the present work the results of interpretation of changes or "kinematics" of load regimes are presented on the basis of a conformal and hyperbolic plane.
Keywords: limited capacity voltage source, boost converter, regulated characteristic, regime determination, projective transformations, hyperbolic geometry
Title of the Paper: A Methodology for Placement-Aware Partitioning
Authors: Wei-Kai Cheng, Tsu-Yun Hsueh, Jui-Hung Hung, Tsai-Ming Hsieh, Mely Chen Chi
Abstract: Circuit partition is the first stage of physical design. As the improvement of semiconductor technique, the number of transistors increases rapidly in a VLSI design. Therefore, how to partition a circuit effectively in order to reduce the design complexity becomes a crucial problem. In this paper, we propose a placement-aware partition methodology to reduce the total wire length after cell placement and global routing. A 2-way partitioning algorithm developed previously has been proved to be effective for the 3D IC partition problem. By the application of 2-way partitioning algorithm and a set of terminal propagation rules proposed in this paper, we can take into account the external interconnections of the target partition region effectively, and calculate the gain of partition precisely, such that the wire length could be minimized. A set of benchmarks from the 2011 ISPD contest are used to test our methodology. Experimental results show that in comparison with previous work, our methodology reduces the total wire length after placement in terms of both HPWL and STWL, and also reduces the real length of routing wires after global routing effectively.
Keywords: Placement-aware partition, terminal propagation, EIA-coarsening, HPWL, STWL
Title of the Paper: Application of High Voltage Ratio and Low Ripple Interleaved DC-DC Converter for a Fuel Cell
Authors: Long-Yi Chang, Kuei-Hsiang Chao, Tsang-Chih Chang
Abstract: This paper proposes a high voltage ratio and low ripple interleaved boost DC-DC converter, which can be used to reduce the output voltage ripple. This converter transfers the low DC voltage of fuel cell to high DC voltage in DC link. The structure of the converter is parallel with two voltage-doublers boost converters by interleaving their output voltages to reduce the voltage ripple ratio. Besides, it can lower the current stress for the switches and inductors in the system. Finally, some experimental results are made to verify the feasibility of the proposed converter.
Keywords: Fuel Cell, High Voltage Ratio DC-DC Converter, Low Ripple, Interleaved Converter
Issue 2, Volume 12, February 2013
Title of the Paper: Novel Powerful Comprehensive Analytical Probabilistic Model of Random Variation in Subthreshold MOSFET’s Performance
Authors: Rawid Banchuin
Abstract: In this research, the novel comprehensive probabilistic analytical model of the subthreshold MOSFET’s performance affected by both random dopant fluctuation and process variation effects has been proposed. The up to dated Takeuchi’s physical level random variation model has been adopted. The proposed model has been found to be analytic, powerful and comprehensive as it has been derived by using the subthreshold MOSFET’s physical equation without any approximation. This model has been verified at the nanometer level i.e. 65 nm CMOS process, by using the BSIM4 based Monte-Carlo simulations. The verifications have been performed based on both NMOS and PMOS technologies. This model is very accurate since it can closely follow the Monte-Carlo based distributions with pleasant goodness of fit test results. Furthermore, the proposed model can also serve as the basis for the mismatch modeling and performance optimization. Hence, the proposed model has been found to be the potential mathematical tool for the statistical/variability aware analysis/design of various subthreshold region operated MOSFET based low voltage/low power.
Keywords: Drain current, low power, low voltage, nanometer level, MOSFET, statistical design, subthreshold, variability aware design
Title of the Paper: Performance Analysis of Novel Domino XNOR Gate in Sub 45nm CMOS Technology
Authors: Amit Kumar Pandey, Ram Awadh Mishra, Rajendra Kumar Nagaria
Abstract: In this paper, three new versions of domino XNOR gate circuits are proposed. The proposed circuits adopt mixed N and P type transistor in the pull-down network. All performance parameters are measured at 25°C and 110°C. In first proposed circuit, it lowers the total leakage power by 8% to 12%, PDP is reduced by 6% to 9% and A.C noise margin is enhanced by 7% as compared to standard n-type XNOR gate. Second proposed circuit having multiple threshold voltage, lowers the total leakage power by 47% to 57%, PDP is reduced by 80% to 86%, and A.C noise margin is enhanced by 33% as compared to standard n-type XNOR gate. Third proposed circuit having multiple power supply, lowers the total power consumption by 56% to 65%, PDP is reduced by 83% to 88% and A.C noise margin is enhanced by 58% as compared to standard ntype XNOR gate.
Keywords: domino logic, gate oxide leakage current, noise margin, multiple threshold voltage, subthreshold leakage current, XNOR gate
Title of the Paper: Applications of Artificial Neural Networks For Regulation of Temperature in a Tank
Authors: Silviya Kachulkova
Abstract: That paper describes the usage of Artificial Neural Networks (ANN) which gives us the advantage in control systems to solve and examine the problems with nonlinearities, complex plant modeling and prediction. One of the objectives of the current project is to develop an integrated control system, which consists of a plant (physical object, which should be controlled) – a liquid heating process, which temperature should be controlled via a real actuator.
Keywords: Ziegler-Nichols models, Artificial Neural Networks, control the temperature of water in a tank, ANN plant predictor, PI controller, Accuracy of the Predictor
Issue 3, Volume 12, March 2013
Title of the Paper: Novel Comprehensive Analytical Probabilistic Models of The Random Variations in MOSFET’s High Frequency Performances
Authors: Rawid Banchuin
Abstract: In this research, the probabilistic models of the random variations in MOSFET’s high frequency performance defined in terms of variations in gate capacitance and transition frequency, have been proposed. Both random dopant fluctuation and process variation effects which are the major causes of the MOSFET’s high frequency characteristic variations have been taken into account. The short channel MOSFET has been focused. The proposed models which take the form of the comprehensive analytical expressions have been derived by using the alpha-power law which is more comprehensive than the conventional square law. The up to dated physical level fluctuation model has been adopted as the basis instead of the classical one. So, the model of gate capacitance variation has been refined. These probabilistic models have been verified based on the IBM 90nm RF CMOS technology by using the Monte-Carlo SPICE simulations and the Kolmogorov- Smirnof goodness of fit tests. They are very accurate since they can fit the Monte-Carlo SPICE based data and distributions with 99% confidence. Hence, the proposed models have been found to be the potential mathematical tool for the statistical/variability aware analysis /design of various MOSFET based high frequency applications.
Keywords: Gate capacitance, High frequency, MOSFET, Short channel, Statistical design, Transition frequency, Variability aware design
Title of the Paper: Explicit Model of Cylindrical Surrounding Double-Gate MOSFET
Authors: Viranjay M. Srivastava, K. S. Yadav, G. Singh
Abstract: We present an analytical and continuous dc model for undoped cylindrical surrounding double-gate (CSDG) MOSFETs for which the drain current and subthreshold model is written as an explicit function of the applied voltages for the wireless telecommunication systems to operate at the microwave frequency regime of the spectrum. The model is based on a unified charge control model developed for this device. This CSDG MOSFET can be used as the RF switch for selecting the data streams from antennas for both the transmitting and receiving processes. We emphasize on the basics of the drain current with drain induced barrier lowering (DIBL) and short channel effects (SCE), for the integrated circuit of the radio frequency sub-system. We analyzed that the drain current is higher, output conductance is lower which shows that the isolation is better in CSDG MOSFET as compared to double-gate MOSFET and single-gate MOSFET. The proposed explicit model satisfies the conformity with the numerical exact solution obtained from the charge control model.
Keywords: Charge control model, Cylindrical surrounding double-gate MOSFET, CMOS switch, Doublegate MOSFET, RF switch, VLSI
Title of the Paper: A Method for Linearization of Optically Insulated Voltage Transducers
Authors: Daniele Gallo, Carmine Landi, Mario Luiso, Edoardo Fiorucci, Giovanni Bucci, Fabrizio Ciancetta
Abstract: In the perspective of a capillary power system monitoring, measurement transducers must have larger and larger bandwidth and accuracy, due to proliferation on power grids of new power quality phenomena. Various types of voltage transducers, based on different operation principles, have been realized; in particular, those based on voltage dividers and optical insulation with digital communication seem to offer suitable features for an accurate disturbance monitoring. Anyway, very often they present high cost, too, and so this strongly limit their diffusion. Optical insulation with analog communication could offer all the desired features: nevertheless it is obtained through non linear devices. So, in this paper a low cost method for linearization of voltage transducers for power systems, based on an optical insulation with analog communication, is presented. The described method is used to implement a prototype of a voltage transducer, whose design, simulation and realization are presented. Experimental characterization has shown that, despite the low cost, the transducer has very good performance, in terms of accuracy, bandwidth and linearity.
Keywords: transducers, voltage measurement, power system measurement, power quality, frequency response, linearization
Issue 4, Volume 12, April 2013
Title of the Paper: JPEG2000 Hardware Implementation - Procedures and Issues
Authors: Ali M. Reza
Abstract: Hardware implementation of JPEG 2000 compression/decompression standard, applicable to the realtime image sequences, is discussed in this article. The general system-level design along with its details are presented. In this work, for clarity and ease of understanding, implementation of lossless and lossy compressions are treated independently. Depending on the application, usually one implementation is preferred over the other and in general there is no need to include both methods on the same hardware platform. For multi-level decomposition, it is assumed that the LL component of the previous stage, i.e., scale-coefficient, is fed back to the same hardware for further decomposition. Lifting approach along with convolution method and polyphase decomposition for implementation of the forward and inverse discrete wavelet transform (DWT) are discussed.
Keywords: JPEG 2000, Hardware Implementation, Discrete Wavelet Transform, Lossy and Lossless Compression, Lifting Algorithm
Title of the Paper: A Fault Detection Method Based on Dynamic Peak-valley Limit under the Non-Steady Conditions
Authors: Tian-Zhen Wang, Man Xu, Tian-Hao Tang, Christophe Claramunt
Abstract: The multivariate statistical methods are commonly used to fault detection through a straight limit line given by the HotellingT2. However, the traditional straight limit line is difficult to detect the fault effectively under the non-steady conditions, and the rate of false alarm and missing alarm is high. For these problems above, a fault detection method based on dynamic peak-valley limit is proposed in this paper. The proposed method introduces relative principal component analysis (RPCA) to carry out data dimension reduction, extract principal component (PCs) and calculate T2 statistics, then adopts moving least squares (MLS) to preprocess T2 statistics to obtain the fitting curve which is called peak-valley curve, and finally connects peak and valley points in the curve to construct another control limit, by introducing a weight combined with the traditional straight limit line to construct the dynamic peak-valley limit. At the end, it is applied to wind power generation system, and the results could verify the effectiveness of the method.
Keywords: T2-statistic, Dynamic Peak-valley Limit, RPCA, MLS, Peak-valley Curve, Fault Detect
Title of the Paper: Second-Degree Polynomial Model of Laser Generation for a CuBr Laser
Authors: Nikolay Denev, Iliycho Iliev, Snezhana Gocheva-Ilieva
Abstract: The subject of investigation is a copper bromide vapor laser, generating laser emissions in the visible spectrum (510.6 nm and 578.2 nm). A statistical model has been developed based on experiment data. The goal is to analyze the state of existing lasers and to predict the behavior of new laser sources. A second-degree polynomial model has been developed to determine output laser generation in relation to 10 independent input laser characteristics. The model describes 96.7% of examined experiment data. An adequacy diagnosis has been performed on the obtained model. The model is applied to predict the output power of the laser source in relation to new data of the input characteristics.
Keywords: Copper bromide laser (CuBr), Laser generation, Second order model, Statistical Prediction model, Multiple linear regression, Factor analysis, Cluster analysis
Issue 5, Volume 12, May 2013
Title of the Paper: A Design Approach for DC Voltage Controller of CHB-based STATCOM
Authors: Xingwu Yang
Abstract: In this paper, a novel parameter design approach of the PI controller used for individual DC voltage balancing control of cascaded H-bridge converter-based STATic synchronous COMpensator(STATCOM) is presented. By means of phase shift sinusoidal pulse width modulation, using two control loops(DC voltage control loop and phase angle shift control loop) to ensure DC voltage balance, the proposed approach can calculate parameters of the PI controller of the two control loops relative accurately by finding the relationship of the input and output of PI controller, The simulation and experimental results verify that the proposed method has good effects of balancing individual DC voltage, meanwhile, it makes the system a good dynamic performance.
Keywords: CHB inverter, Static synchronous compensator (STATCOM), DC voltage controller, parameter design, Sinusoidal pulse width modulation
Title of the Paper: Stabilization of DC Link Voltage Using Redundant Vectors for Five-Level Diode Clamped Shunt Active Power Filter
Authors: Thameur Abdelkrim, Karima Benamrane, Tarak Benslimane, Abdelhak Benkhelifa
Abstract: In this paper, the control of DC link capacitor voltages of five-level diode clamped Active Power Filter (APF) using simplified Space Vector Pulse Width Modulation (SVPWM) associated with the redundant vectors of this topology is proposed. The space vector diagram of the five-level inverter is simplified into that of three-level inverter. In turn, the three-level inverter space vector diagram is simplified into that of two-level inverter. Thus, the algorithm of five-level SVPWM becomes very similar to that of conventional two-level inverter SVPWM. Concerning the self stabilization of dc link capacitor voltages, on the base of position of reference voltage vector in space vector diagram, we explain how to choose switching states that will be used to generate the output voltages. The redundancies of some switching states are thoughtfully used to cancel imbalance of dc link capacitor voltages, on the base of a closed loop that use measurements of input and output currents of the APF. The performance of the proposed redundant vector algorithm associated with sliding regulator used to control the shunt APF is illustrated through the compensation of harmonic currents and reactive power produced by a non-linear load in medium voltage network.
Keywords: Active Power Filter, Harmonic current, Five-level inverter, Space Vector Pulse Width Modulation (SVPWM), DC source balancing, Redundant vectors
Title of the Paper: Hybrid Power System with A Two-Input Power Converter
Authors: Y. L. Juan, H. Y. Yang
Abstract: An isolated two-input power converter for hybrid power supply systems is proposed in this paper. The proposed converter is derived from the integration of a forward converter and a Cuk converter. The grid and solar energy are used as the two input power sources. The power flow of each energy source can be independently controlled. Also, the proposed converter can be operated with single power source or dual power sources. Once the maximum available solar power is insufficient for the load, the converter would automatically complement the power demand by drawing power from the grid side. A prototype system is constructed and some experiments are carried out to evaluate the validity and performance of the proposed twoinput power converter. From the experimental results, one can see that the proposed converter can provide a stable output with 90V /3.85A and the efficiency is about 90%.
Keywords: Two-input power converter, Hybrid power supply, solar energy
Issue 6, Volume 12, June 2013
Title of the Paper: Assembling of the SC Circuit Matrix Based on the Status of Switches
Authors: Bohumil Brtník
Abstract: This paper deals with assembling of the SC circuit matrix based on the status of switches. It is well known matrix assembly process using two-graphs or transformation graphs. However, the matrix can be built only on the basis of the status switches in the SC circuit. This procedure is somewhat simpler than the method of two-graphs. Described method is compared with other methods, too.
Keywords: SC circuit, status of switches, nodal charge method, capacitance matrix, four phases of switching
Title of the Paper: Analysis of Stability for Impulsive Stochastic Fuzzy Cohen-Grossberg Neural Networks with Mixed Delays
Authors: Qianhong Zhang, Jingzhong Liu, Yuanfu Shao
Abstract: In this paper, the problem of stability analysis for a class of impulsive stochastic fuzzy Cohen-Grossberg neural networks with mixed delays is considered. Based on M-matrix theory and stochastic analysis technique, a sufficient condition is obtained to ensure the existence, uniqueness, and global exponential stability in mean square means of the equilibrium point for the addressed impulsive stochastic fuzzy Cohen-Grossberg neural network with mixed delays. Moreover an illustrative example is given to demonstrate the effectiveness of the results obtained.
Keywords: Fuzzy Cohen-Grossberg neural networks, Global mean square exponential stability, Mixed delays, Impulses, Ito differential formula
Title of the Paper: Multi-Output Auxiliary Power Supply with Lossless Snubber
Authors: Geeng-Kwei Chang, Shu-Yuan Fan, Sheng-Yu Tseng
Abstract: A multi-output auxiliary power supply realized by a flyback converter is presented for providing the essential low power supplies for control circuits and driving circuits in power processing systems. In the proposed circuit topology, lossless snubbers are introduced into the flyback converter to recover energy trapped in leakage inductor of transformer, and as a result, smoothes out voltage surge across drain-source of the switch, and alleviates oscillation caused by parasitic capacitance of the switch and leakage inductance of the transformer, hence reduces switching losses and improves conversion efficiency. Based on these concepts, an auxiliary power supply with five sets of output voltage has been designed and implemented to verify the feasibility of the proposed multi-output auxiliary power supply. Experimental results show that the conversion efficiency has been increased about 5% and reached 82.5% under full load as compared with flyback converter with hardswitching.
Keywords: Flyback converter; lossless snubber; auxiliary power supply
Issue 7, Volume 12, July 2013
Title of the Paper: Preliminary Structure of Quasi Optimal Algorithm for Optimization of Analog Circuits
Authors: Alexander Zemliak, Tatiana Markina
Abstract: The methodology of designing of analog circuits, being based on applications of control theory is basis for constructing of optimum or quasi optimal algorithm of designing. By a major criterion here, allowing to exposing the necessary structure of algorithm, there is a behavior of function of Lyapunov, which was defining for the process of optimization of circuit. Characteristics of function of Lyapunov and its derivative are basis for the search of optimum structure of control vector determining the structure of algorithm. The flow diagram of quasi optimal algorithm, realizing the basic ideas of the methodology is built, and basic characteristics of this algorithm are presented by comparison to traditional approach.
Keywords: Time-optimal design algorithm, control theory, Lyapunov function, quasi optimal algorithm
Title of the Paper: Multi-Resolution Analysis Wavelet PI Stator Resistance Estimator for Direct Torque Induction Motor Drive
Authors: Ehab H. E. Bayoumi
Abstract: To improve the overall dynamic performance of induction motor in direct torque control (DTC), a novel method of stator resistance estimation based on multi-resolution analysis wavelet PI controller is presented. This estimation method is anchored in an on-line stator resistance correction regarding the variation of the stator current estimation error. The main purpose is to adjust precisely the stator resistance value relatively to the evolution of the stator current estimation error gradient to avoid the drive instability and ensure the tracking of the actual value of the stator resistance. The multi-resolution wavelet controller process the error input with the gains depending on the level of decomposition employed. In order to limit the number of gains, this paper analyzes multi-resolution wavelet controller with a single gain constant. A separate fractional order integrator unit which enhances the controller performance with additional flexibility of tuning and also offers better steady state performance of the motor is introduced. The simulation results show that the proposed method can reduce the torque ripple and current ripple, superior to track the actual value of the stator resistance for different operating conditions.
Keywords: Direct Torque Control, multi-resolution wavelet analysis, PI Controller, Stator Resistance Estimator
Title of the Paper: A New Control Strategy for DFIG Wind Farm with VSC-HVDC Integration
Authors: Yong Liao, Guodong Wang
Abstract: This paper proposes a new control strategy for a doubly-fed induction generator (DFIG) wind farm with VSC-HVDC integration to ensure a secure and reliable operation of the whole system. Based on a virtual voltage orientation, a steady-state voltage control block and a dynamic voltage control block with a cross-product term of d-q currents are separately designed for wind-farm-side VSC (WFVSC) to control the wind farm voltage. Meanwhile, with the consideration of ac and dc side parameters variation and external disturbance, an improved backstepping control scheme with Lyapunov stability proof is designed for the grid-side VSC (GSVSC). To validate the proposed control strategy, three different simulation cases with consideration of system parameters variation and external disturbances are introduced, and numerical simulation results for a 200MW DFIG wind farm with VSC-HVDC integration confirm that the proposed control strategy is of great satisfactory operation performance.
Keywords: Doubly fed induction generator (DFIG), voltage source converter (VSC), high voltage dc transmission (HVDC), wind farm, backstepping, Power quality
Issue 8, Volume 12, August 2013
Title of the Paper: Quadrature Hybrid Miniaturization on Single-Layer Substrate
Authors: Monthippa Uthansakul, Peerapong Uthansakul
Abstract: This paper presents an exact design technique to obtain formulas for compact quadrature hybrid coupler. We minimize the physical size based on even-and odd mode analysis. The proposed structure is relatively simple as the coupler can be fabricated on a single-layer printed circuit board. After finishing the design, full prototype of proposed coupler is fabricated and tested to validate the design. The obtained results reveal that we can reduce the coupler size up to 60% from the conventional one while maintaining its characteristics such as return loss, insertion loss and phase difference between through and coupled ports.
Keywords: Even-odd mode; quadrature hybrid coupler; miniaturization; 3G and LTE
Title of the Paper: An Off-Chip ESD Protection Strategy for High-Speed USB Interfaces
Authors: Jing-Min Wang, Chun-Ting Lin
Abstract: The electrostatic discharge (ESD) is one of the most important reliability problems in an electronic product. For Universal Serial Bus (USB) is a hot insertion and removal interface, its components are easily subject to ESD damage. This work focuses on the influence of the using of USB in plugging and/or unplugging impact arisen from ESD. Employing the off-chip protection technique and commercial protection products, the paper proposes an ESD Protection Strategy for USB (EPSU) to effectively enhance ESD robustness. The comparisons among these ESD protection designs are also discussed. Numerous experiments have been made, the EPSU is around 39.6% more efficient for improving the power trace test, 38.7% for the signal trace D+ test, 41.2% for the signal trace D- test, 39.0% for the GND test, and 39.9% for the shield test. All the ESD tests are complied with the test standard of IEC61000-4-2. To conclude, not but the least of USB, the protection strategy can also be applied to some other USB related electronic products.
Keywords: Electrostatic discharge (ESD), High-speed USB interfaces, EPSU, Off-chip ESD protection, ESD robustness, 61000-4-2 standard
Title of the Paper: Tracking Control of the Maximum Power Point (MPPT) In A Small Wind Turbine (SWT) For Isolated Residential Applications
Authors: David R. López Flores, José A. Pineda Gómez, Roberto Herrera S., Marcelino S. Alvarado, José A. Duarte Moller
Abstract: This work shows the design, analysis, simulation and implementation of a tracking control Maximum Power Point (MPPT) in a Small Wind Turbine (SWT) with fixed angle α. The MPPT controller extracts the maximum available kinetic energy of the wind V, which is converted to mechanical power Pm by the wind rotor shaft, followed by an electrical power Pe . Permanent Magnet Synchronous Generator, (PMSM), and a current three-phase rectifier alternating AC-DC, direct current, voltage Vr generated converter is regulated by a reducer to DC-DC optimal load to maintain a deep cycle battery, using a Proportional Integral controller (PI) and equations relate V, Mn, Vr and angular velocity of the wind rotor W optimizing the output voltage Vr * to maintain maximum energy extraction from the wind at any speed and load demand. A DC-DC boost converter with a PI controller and DC-AC inverter provides AC voltage with low harmonic distortion for residential applications.
Keywords: Tracking system control, MPPT, SWT
Issue 9, Volume 12, September 2013
Title of the Paper: A Data Adaptation Approach for a HW/SW Mixed Architecture (Case Study: 3D Application)
Authors: Tarek Frikha, Nader Ben Amor, Khaled Lahbib, Jean-Philippe Diguet, Mohamed Abid
Abstract: This Embeddd systems use emerges in the electronic field. Many applications have been embedded such as network, image processing, signal processing … The emergency of multimedia applications particularly in mobile embedded systems puts new challenges for the design of such systems. The major difficulty is the embedded system’s reduced computational resources that must be carefully exploited to execute variable workload due to many parameters such as data. In this paper, we propose an adaptive architecture based on dynamical partially reconfigurable approach that manages the system architecture complexity according to the data variability. The augmented reality application is the case study application to confirm the proposed approach.
Keywords: Data adaptation, dynamical partially reconfiguration, augmented reality, 3D application, hardware accelerator, hardware software adequacy
Title of the Paper: Rank-Based Ant Colony Algorithm for a Thermal Generator Maintenance Scheduling Problem
Authors: Aristidis Vlachos
Abstract: The maintenance scheduling of thermal generators is a large-scale combinatorial optimization problem with constraints. In this paper we introduce the Rank-Based Ant System algorithm based version of the Ant System. This algorithm reinforces local search in neighborhood of the best solution found in each iteration while implementing methods to slow convergence and facilitate exploration.Rank-Based Ant System (RBAS) algorithm has been proved to be very effective in finding optimum solution to hard combinational optimization problems . To show its efficiency and effectiveness, the proposed Rank-Based Ant System algorithm is applied to a real-scale system, and further experimenting leads to results that are commented.
Keywords: thermal generator maintenance scheduling problem, ant colony optimization, ant system, rank-based ant system algorithm
Title of the Paper: Behavioral Model of Hydrogen Bonding Network for Digital Signal Processing
Authors: Elitsa Emilova Gieva, Rostislav Pavlov Rusev, George Vasilev Angelov, Rossen Ivanov Radonov, Tihomir Borisov Takov, Marin Hristov Hristov
Abstract: A circuit schematic is extracted from β-lactamase protein hydrogen bonding network. The circuit is consisting of block-elements that functionally represent the hydrogen bonds. The behavioral description of each block element is represented by polynomials. Polynomials and electric connections between the elements are coded in Matlab and Verilog-A. DC, transient, and digital analyses are performed. Simulations proved that the circuit can process digital signals and behaves similarly to current mirror, amplifier, and inverter.
Keywords: Hydrogen bonding network, behavioral modeling, Verilog-a, proteins, β-lactamase
Issue 10, Volume 12, October 2013
Title of the Paper: Epidemic Network Failures in Optical Transport Networks
Authors: Sarah Ruepp, Dimitrios Katsikas, Anna M. Fagertun
Abstract: This paper presents a failure propagation model for transport networks which are affected by epidemic failures. The network is controlled using the GMPLS protocol suite. The Susceptible Infected Disabled (SID) epidemic model is investigated and new signaling functionality of GMPLS to support epidemic failure resolution is proposed. The results provide important input to service recovery mechanisms under epidemic failures.
Keywords: resilience, transport networks, epidemic failures, network modelling, GMPLS, performance evaluation
Title of the Paper: A Novel and Systematic Approach to Implement Reversible Gates in Quantum Dot Cellular Automata
Authors: P. Saravanan, P. Kalpana
Abstract: Quantum dot cellular automata (QCA) is one of the emerging technologies in the area of nanoelectronics and is found to be an attractive alternative to conventional CMOS technology for several reasons. However, there have been no reports in the literature so far on QCA implementation of conventional reversible gates. In this work, we propose a novel and systematic approach for the QCA implementation of conventional reversible gates. The proposed method utilizes universal nature of the majority gate for its operation. The combination of reversible logic synthesis and its QCA implementation proves to be a superior solution for side channel attack based on power analysis in security applications. This is mainly due to the negligible amount of power consumption in both reversible logic and QCA implementation. Hence in this work, a dualfield adder, which plays a vital role in unified architectures of public-key crypto system, has been synthesized in reversible logic and implemented in QCA.
Keywords: Quantum dot cellular automata, Reversible logic, Side channel attack, Nano-technology, Cryptography, Reversible gates
Title of the Paper: A Proposed Eleven-Transistor (11-T) CMOS SRAM Cell for Improved Read Stability and Reduced Read Power Consumption
Authors: Ajay Kumar Singh, Mah Meng Seong, C. M. R. Prabhu
Abstract: Due to scaling of MOS devices, SRAM read stability imposes a serious concern for future technology. The conventional 6T cell becomes more vulnerable to external noise due to voltage division between the access and the pull-down transistors in the inverter. This paper discusses the design and implementation of 11-T SRAM cell to improve the read stability and read power reduction. During read operation storage nodes are completely isolated from the bit lines. The average read power consumption reduces approximately 12% compared to the 6T cell due to lower discharging activity at read bitline and low leakage current. The standby power consumption in the proposed cell is larger than the 6T cell which can be reduced by using minimum size transistors. The read signal noise margin (RSNM) is enhanced by 2x compared to the 6T cell due isolation of read and write circuits. The proposed cell is capable of operating at a supply voltage as low as 330mv and can be used in ultra-low power circuit applications.
Keywords: SRAM cell, read stability, SNM, power consumption, read/write access time, leakage current
Issue 11, Volume 12, November 2013
Title of the Paper: Testing of N-Stage 1 Bit Per Stage Pipelined ADC Using Test Input Regeneration
Authors: S. M. Hamed, A. H. Khalil, M. B. Abdelhalim, H. H. Amer, A. H. Madian
Abstract: Analog-to-Digital Converters (ADCs) became an integral part in most systems. The Pipelined ADC (PADC) is one of the preferred ADCs; it is perfect for applications requiring high speed and medium resolution. Hence, the test of ADCs in general as well as PADCs is not only interesting but mandatory; the need for a low cost and efficient test technique in order to test the PADC is increasing. The focus in this paper is on proposing a new efficient test technique fitting an N-stage PADC test. The proposed technique depends on the selection of test inputs that can be applied to the first stage of the PADC and it is guaranteed that they can be regenerated at the input of next stages in the PADC. This proposed technique does not use complex hardware and there is no need to access the input or output of each individual stage. It will be shown that only two DC test inputs are able to detect all catastrophic faults in the N-stage PADC producing 100% fault coverage. The simulation results are based on circuit-level simulations using the Eldo simulator provided by Mentor Graphics.
Keywords: PADC, Test Input Regeneration, N-stage, Catastrophic, Fault model, Structural test
Title of the Paper: Investigations on AQ-DBPSK Modulation based RF Transceiver for Wireless Sensor Communication Networks
Authors: Vasanthi M. S., Rama Rao T.
Abstract: This research work demonstrates the simulation results of a Radio Frequency (RF) transceiver with Alternate Quadrature Differential Binary Phase Shift Keying (AQ-DBPSK) modulation at 2.4GHz. The RF transmitter consists of an AQ-DBPSK modulator, an up conversion mixer, a 2.4 GHz Band pass filter and a power amplifier. At the receiver RF front end, the Low Noise Amplifier (LNA), mixer with down conversion to Intermediate Frequency (IF), a Low Pass Filter (LPF) and an AQ-DBPSK demodulator is used. The block level parameters of the transmitter and receiver RF front end like Noise Figure (NF) and Gain are optimized to meet the transceiver specifications for the applications in Wireless Sensor Communication Networks.
Keywords: AQ-DBPSK, Energy Efficient Modulation, RF Transceiver, Transmitter Efficiency, Wireless Sensor Communications
Title of the Paper: Based on Negotiation Strategies and Dynamic Learning Model Generation Rights Trade
Authors: Xie Chuansheng, Zhou Chengying, Li Yulong
Abstract: The accelerating development of China has meanwhile induced some negative issues, such as energy and environmental problems. This paper has brought Generation rights trade into the current electricity market environment, which not only effectively alleviate the contradictions arising from rapid development, but also enable the generation right buyers and sellers to achieve their mutual profit maximization. According to the general trading psychology, both sides expect the price close to their expected price in order to maximize their profits.Thus by establishing the electricity market transaction negotiation model, buyers and sellers estimate rival’s price bottom line via past experience, and also implement the dynamic learning of random disturbance term with the help of symmetry information during transaction process, and then reacquaint the rival’s bottom line. After that both sides make decision optimization by using Zeuthen decision to test the wind resistance of buyers and sellers, and each makes its most beneficial offer decisions. Finally, both sides reach to the final offer through repeated negotiation. The simulation results show that the transaction price is comparatively consistent with the ideal price, and also the transaction price is close to the optimal solution of Nash plot.
Keywords: power trading, decision optimization, dynamic learning, transaction risk
Issue 12, Volume 12, December 2013
Title of the Paper: Slots Geometry Influence on the Air Gap Magnetic Field Distribution
Authors: Bellal Zaghdoud, Abdallah Saadoun
Abstract: Prediction and performance analysis of electrical machines depend mainly on the accuracy in the evaluation of the magnetic field linking the different parts of the machine. This paper presents the influence of the slots geometry on permanent magnet synchronous machine (PMSM) magnetic field distribution using finite element method (FEM), where we change the slots structure in order to improve the air gap magnetic field distribution .The accuracy of the developed model is verified by comparing its results with those obtained from experimental measurements.
Keywords: Air-gap, slots effects, finite element, magnetic field, permanent-magnet, synchronous motor
Title of the Paper: High Voltage Pulse Generator by Connecting Normal Coaxial Cables in Series and in Parallel without Using Blumlein Method
Authors: Hitoshi Kijima, Koji Ochi
Abstract: In order to carry out the simulation of the electrical noise, a pulse generator with fast rise time is needed. For this reason, the pulse generator using a coaxial cable is usually used. The pulse generator consists of a DC power supply, a charging resistor, a coaxial cable, a relay, and a terminator. Even the same voltage as charge voltage was outputted when the termination of the impedance was high, only the output of the half of charge voltage is obtained when the termination impedance was set at 50 ohm which is the characteristic impedance of the coaxial cable. For this reason, we have been developing a pulse generator with the same voltage as charge voltage while termination impedance was set at 50 ohm, by connecting four coaxial cables in series and in parallel.
Keywords: Impulse, Transmission Line Pulse, Noise immunity test, Coaxial cable, Blumlein method, Mercury relay
Title of the Paper: Design of 4-Bit Reversible Shift Registers
Authors: A. V. Ananthalakshmi, G. F. Sudha
Abstract: In recent years, Reversible logic has emerged as a major area of research due to its ability to reduce the power dissipation which is the main requirement in the low power digital circuit design. It has wide applications like low power CMOS design, Nano-technology, Digital signal processing, Communication, DNA computing and Optical computing. In this paper, we have proposed a new 4x4 reversible gate and it is being used to realize the D-latch and D-flip-flop in the reversible domain. The transistor representation of the proposed reversible D-flip-flop is implemented using adiabatic logic. Also a 4-bit reversible SISO, SIPO, PISO and PIPO shift registers has been designed using the proposed reversible d-flip-flop. Proposed circuits have been simulated using Modelsim and synthesized using Xilinx Virtex5vlx30tff665-3.
Keywords: Reversible D-Latch, Reversible D-Flip-Flop, Reversible Shift Registers, FPGA