WSEAS Transactions on Circuits and Systems

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Print ISSN: 1109-2734
E-ISSN: 2224-266X

Volume 14, 2015

Notice: As of 2014 and for the forthcoming years, the publication frequency/periodicity of WSEAS Journals is adapted to the 'continuously updated' model. What this means is that instead of being separated into issues, new papers will be added on a continuous basis, allowing a more regular flow and shorter publication times. The papers will appear in reverse order, therefore the most recent one will be on top.

Volume 14, 2015

Title of the Paper: DSLR Camera Immunity to Electromagnetic Fields – Experiment Description

Authors: Martin Pospisilik, Tomas Riha, Milan Adamek, Rui Miguel Soares Silva

Abstract: Currently, the issues of electromagnetic compatibility have become important due to the increasing number of electronic devices that share common space. An important part of this field is the area of electromagnetic susceptibility that studies how a tested device can withstand the interferences caused by other devices in its neighbourhood. As it is generally known that CCD sensors of photo cameras can also be affected by external electrical field as they use their own electrical field in order to transport the electrons generated in their structure, the authors of this paper decided to process a test of electromagnetic susceptibility on a DSLR photo camera Nikon D40. The configuration of the test as well as the obtained results are described within this paper.

Keywords: Electromagnetic susceptibility, Electromagnetic compatibility, Photo camera, Semianechoic chamber

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #57, pp. 495-505

Title of the Paper: Composite Second Generation Current Conveyor Based Tunable MOS-C Quadrature Sinusoidal Oscillator Design and Comparative Performance Analysis

Authors: Hasan Çiçekli, Ahmet Gökçen

Abstract: In this paper, a new voltage mode tunable MOS-C quadrature sinusoidal oscillator circuit employing composite second-generation current conveyor (CCCII) is presented. The proposed topology employs two CCCII and four grounded components. CCCII is implemented by using two CCIIs as sub-circuit. This implementation technique makes it possible to employ the circuit by commercially available integrated circuits that can be used as current conveyor such as AD844. The validity of the proposed circuit is verified by PSPICE simulation program. Simulation is performed for both CMOS based CCCII using MOSIS 0.35 μm process parameters and AD844 based CCCII using the Spice Macromodel parameters of AD844. It is seen that the simulation results agree well with the theoretical analysis and the proposed circuit achieves a good THD performance. The resistors used in the circuit are implemented by using MOS transistors. So, the proposed circuit is fully integrable and oscillation frequency can be tuned by external MOS gate voltages. Also, a comparative performance analysis is performed for the two circuits employing CCII and CCCII which are belong to the same topology. It is stated that employing CCCII improve the circuit performance significantly when compared to the same topology employing CCII for both CMOS and AD844 based implementations.

Keywords: Analog integrated circuits, Current conveyors, MOS-C realization, Quadrature sinusoidal oscilltors

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #56, pp. 489-494

Title of the Paper: A novel design process of low cost 3D printed ambidextrous finger designed for an ambidextrous robotic hand

Authors: Emre Akyürek, Tatiana Kalganova, Mashood Mukhtar, Luke Steele, Michal Simko, Alisdair Nimmo, Luke Kavanagh, Leonid Paramonov, Anthony Huynh, Stelarc

Abstract: This paper presents the novel mechanical design of an ambidextrous finger specifically designed for an ambidextrous anthropomorphic robotic hand actuated by pneumatic artificial muscles. The ambidextrous nature of design allows fingers to perform both left and right hand movements. The aim of our design is to reduce the number of actuators, increase the range of movements with best possible range ideally greater than a common human finger. Four prototypes are discussed in this paper; first prototype is focused on the choice of material and to consider the possible ways to reduce friction. Second prototype is designed to investigate the tendons routing configurations. Aim of third and fourth prototype is to improve the overall performance and to maximize the grasping force. Finally, a unified design (Final design) is presented in great detail. Comparison of all prototypes is done from different angles to evaluate the best design. The kinematic features of intermediate mode have been analysed to optimize both the flexibility and the robustness of the system, as well as to minimize the number of pneumatic muscles. The final design of an ambidextrous finger has developed, tested and 3D printed.

Keywords: Ambidextrous finger, Finger design process, Low cost 3D printed finger, Ambidextrous finger concept, Robotic finger design

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #55, pp. 475-488

Title of the Paper: Design of Many Core Interrupt Controller Based on ARMv8 Architecture

Authors: Bing Li, Jun Lu, Dezhi Wu, Guanyu Liu

Abstract: This paper presents a design of many core interrupt controller based on ARMv8 architecture, which is known as Generic Interrupt Controller (GIC). Interrupt controller is one of the most important peripheral modules, which affects the performance of microprocessor directly. GIC deals with all the interrupt requests and sends interrupt requests to the each processor, which is connected to the GIC. This design of GIC adopts the principle of hierarchical coding to choice the interrupt which has the highest priority. supports 64 cores, 16 priority levels, level 7 interrupt preemption. After analyze of GIC signature, this paper presents a realization of GIC. Proposed GIC has been verified under Modelsim software and FPGA development board, and the simulation result is consistent with the expectations. Use DC to synthesis GIC with the condition of 40nm process library, 1 GHz, and the timing meet the requirement and the total area is 111490 μm2.

Keywords: ARMv8 architecture, GIC, interrupt controller, many core, AXI, interrupt

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #54, pp. 469-474

Title of the Paper: G-MPSoC: Generic Massively Parallel Architecture on FPGA

Authors: Hana Krichene, Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser

Abstract: Nowadays, recent intensive signal processing applications are evolving and are characterized by the diversity of algorithms (filtering, correlation, etc.) and their numerous parameters. Having a flexible and programmable system that adapts to changing and various characteristics of these applications reduces the design cost. In this context, we propose in this paper Generic Massively Parallel architecture (G-MPSoC). G-MPSoC is a System-on-Chip based on a grid of clusters of Hardware and Software Computation Elements with different size, performance, and complexity. It is composed of parametric IP-reused modules: processor, controller, accelerator, memory, interconnection network, etc. to build different architecture configurations. The generic structure of GMPSoC facilitates its adaptation to the intensive signal processing applications requirements. This paper presents G-MPSoC architecture and details its different components. The FPGA-based implementation and the experimental results validate the architectural model choice and show the effectiveness of this design.

Keywords: SoC, FPGA, MPP, Generic architecture, parallelism, IP-reused

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #53, pp. 457-468

Title of the Paper: A Design and Implementation of Custom Communication Protocol Based on Aurora

Authors: Bing Li, Jiajin Zhang, Shuiling Yan, Wei Shao

Abstract: This paper presents the design and implementation of a new custom communication protocol based on Aurora combining PCI Express bus. This design can be applied to the transmission and forward of data among multiple nodes in the network. This custom protocol uses serial connection and transfer data in the form of packet. This custom protocol is divided into four layers, respectively the transaction layer, network layer, data link layer and Aurora layer. The retransmission and flow control mechanism are introduced to guarantee the correctness and completeness of the data transmission, and the network layer supports the interconnection of multiple nodes and rapid forwarding of data. This design is verified successfully on the Modelsim simulation platform and completes the FPGA board level test. The device mode is XC7VX485T and the package is ffg1761. The serial transmission rate can achieve 10Gbps on the FPGA board.

Keywords: Aurora protocol, PCI Express, custom protocol, Packet, Node, FPGA

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #52, pp. 449-456

Title of the Paper: A Magnetic Resonant Coupling Printed Spiral Coil System under Different Geometric Values

Authors: Hanqiu Mo, Houjun Tang

Abstract: Recently, the wireless power transfer (WPT) technology is attracting attention widely because of the expanding use of portable devices. In WPT system, the coil formed on printed circuit board is used because it could be modified easily and captured in printed circuit board conveniently. A lot of studied have been proceeded to improve the power transmission efficiency. However, the optimum of coils geometric parameters on performance of coil system has not been fully explored yet. Consequently, three geometric parameters of printed square coil have been investigated for the effect on the power transmission efficiency coils while the other geometric parameters are remaining constant. As a result, we found that the optimum transmission efficiency improved by adjusting the width of copper wire, the pitch between adjacent wire and the thickness of wire. Moreover, a printed spiral coil board system has been designed and simulated based on the analysis above. The total power transfer efficiency is over 85% at 10mm equaling to half of coils diameter.

Keywords: Magnetic resonant, Wireless power transmission, Q factor, Optimum power transmission efficiency, Geometric value

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #51, pp. 443-448

Title of the Paper: Design of Nonlinear Optimal Control Systems Using Jordan Controlled Form

Authors: Anatoly Gaiduk

Abstract: The problem of control systems design for nonlinear plants still has no exhaustive solution. This problem is commonly solved on the basis of transformation of the nonlinear plant equations to some simple. Such approach simplifies the solution of the control system design problem and makes the solution analytical. For design of the optimal control systems for the nonlinear plants, their equations are expedient to transform to Jordan controlled form (JCF). The analytical design method of the optimal control systems for nonlinear plants with using the JCF of their equations is proposed in this paper. This problem has a solution if all plant state variables are measured. The JCF exists, if the nonlinear plant is completely controllable. The proposed method includes two steps. At the first step, a linearization control is designed by a nonlinear reversible transformation of the plant state variables. Under the linearization control, the system equations are linear and stationary in the new variables. Theorem about existence of a linearization control is proved. At the second step, the optimal control is designed as optimal in the sense of a minimum of nonlinear quadratic criteria. This control is designed using solution of the Riccati equation. Optimality of the obtained nonlinear control is proved also. Design of the optimal control systems for nonlinear plants using JCF is expedient, because the equations of many real plants have JCF or can be easily transformed to this form. Frequently, the plant equations convert into this form if the state variables are designated in appropriate way. The example of the optimal control system design for nonlinear plant is given.

Keywords: Nonlinear plant, reversible transformation, Jordan controlled form, linearization control, optimal control, nonlinear quadratic criteria

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #50, pp. 436-442

Title of the Paper: Study on Risk Analysis of Railway Signal System

Authors: Yuanyuan Li, Youpeng Zhang, Rang Hu

Abstract: Railway signal system requires the high level of safety in order to safeguard safe operation of the train and people’s lives, so the risk analysis of railway signal system counts for much. However, due to the incomplete of the risk data, it is often impossible to obtain a satisfactory result. This article presents a comprehensive study in the risk analysis model of railway signal system on safety risks. In this methodology, evidential reasoning is employed to synthesizing the experts’ opinions thus produced to determine the relative importance of the risk contributions. This allows uncertain information in the risk analysis process. Then, weighted and risk factor values are converted to the matrixes represented in numerical features via the cloud model. Finally, the risk level is obtained by using the weighted average integrated function. Also, a practical case study on risk analysis of computer interlocking system is presented to demonstrate the application of the proposed risk analysis, and the result shows that the method is not only suitable for risk analysis method, but also is able to find out the weak links in railway signal system. What is more, it provides a new foundation for the risk analysis of railway signal system.

Keywords: Railway signal system, Risk analysis, Computer interlocking system, Evidential reasoning, Cloud model

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #49, pp. 428-435

Title of the Paper: Safety Analysis on Regional Computer Interlocking System Based on Dynamic Fault Tree

Authors: Hongsheng Su, Jun Wen

Abstract: Regional Computer Interlocking System (RCIS) is a signal control system which performs all interlocking logic operation and implements centralized control for multiple stations only using one set of interlocking equipment. Recently, the main method to analyze safety of dynamic redundancy systems structure is based on the Markov model at home and abroad. But in applying the Markov model to analyze the safety of regional computer interlocking system, the size of state space is quite larger such that the modeling and solving processes become very complex. To solve this issue, in this paper, Dynamic Fault Tree (DFT) model of RCIS is established from the perspective of system failure, and probabilistic approximation method is used to solve the probability of falling safety (PFS) and probability of falling danger (PFD). Eventually, a comparison is conducted between DFT probabilistic approximation method and Markov method. The relative researches show that DFT probabilistic approximation method possesses roughly same outcome with ones of Markov method, and tends to be more conservative in calculating probability indexes, which provides a new solution for complex dynamic redundancy system safety analysis.

Keywords: Regional Computer Interlocking System(RCIS), Dynamic Fault Tree(DFT), Probabilistic approximation method, Probability of falling safety(PFS), Probability of falling danger(PFD)

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #48, pp. 415-427

Title of the Paper: Harmony Search Based PID for Multi Area Load Frequency Control Including Boiler Dynamics and Nonlinearities

Authors: M. Omar, M. A. Ebrahim, A. M. Abdel Ghany, F. Bendary

Abstract: This paper proposes a new Artificial Intelligence technique known as Harmony Search (HS) for optimal tuning of PID controllers for Load Frequency Control (LFC). The system proposed here is a three area with reheat thermal system containing nonlinearities represented by Generation Rate Constraint (GRC), Dead Band and Boiler Dynamics. The proposed system has been chosen especially to mimic typical system behaviour in actual operation. Four different generations (versions) of HS have been used for tuning the PID controllers. The closed loop response of the system using the optimized PID gains has been compared with another one tuned by Genetic Algorithm (GA). Simulation results significantly verify that the sample controller can favourable performance and contribute efficiently enhancing the system dynamic behaviour.

Keywords: Harmony search, Load Frequency Control, PID controller, Objective Function

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #47, pp. 407-414

Title of the Paper: Study on Shunt State of Track Circuit Based on Transient Current

Authors: Qi Huan,Zhang You-Peng, Zhao Bin

Abstract: Track circuit is considered to be one of the means of train detection, its shunt state often misjudged due to the shunt malfunction. Aim at the influence of shunt malfunction on the shunt state of track circuit, a detection method for the shunt state of track circuit according to the transient current was proposed. And the time response of track circuit was obtained by the precise time-integration method. The truncation error is efficiently decreased by interlacing the voltage and current nodes along the x-axis. Taking the boundary conditions of track circuit in adjusting and shunting state, changes of the receiving end current was simulated. The results show that the precise time-integration is unconditional stability, which is an effective method for analysis of track circuit and the transient current when a train entering or clearing a track section, which can be regard as an important information for the shunt state of track circuit.

Keywords: track circuit, shunt state, transient current, precise time-integration method, stability

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #46, pp. 400-406

Title of the Paper: Power Quality Analysis of Domestic Lamps Available in the Brazilian Market

Authors: Antônio Marcos Estrela Pereira, Victor Argemil Teixeira, Márcio Zamboti Fortes, Geraldo Martins Tavares, Vitor Hugo Ferreira

Abstract: Different economic sectors have attempted to find solutions to mitigate the effect of the global energy crisis. Reducing energy consumption in its various forms is necessary, due to economic and environmental reasons, among others. The rational use of energy is one solution to this problem. It is estimated that 20% of Brazil’s residential electricity consumption is spent on lighting. Thus, replacing lamps of high consumption by more efficient light bulbs is one method to reduce energy consumption. This paper presents a comparison of energy efficiency indicators among domestic lighting lamps available in the Brazilian market, specifically, incandescent bulbs, compact fluorescent lamps (CFLs), and light emitting diode lamps (LEDs). Despite this activity (exchange of lamps technology) is widespread in many countries, it is important for researchers to analyze in detail what is being offered in the local market and if the policies and equipment standardization are being met by lighting equipment suppliers. This paper presents and compares results based on an analysis of some power quality criteria (without going into details in rectifier circuits used). This research can be applied to similar products in any country or region, and it can support other researches related to the real impact of new lighting technologies in order to reduce energy consumption in residential buildings (as presented) and others buildings.

Keywords: new lighting technologies, energy quality, energy efficiency, lamps, energy measurement

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #45, pp. 389-399

Title of the Paper: Implementing Complex Wavelet Transform in Analog Circuit and Singular Value Decomposition Algorithm

Authors: Mu Li, Yigang He, Xiaofeng Wu, Zaifang Xi

Abstract: A new method for implementing complex wavelet transform (CWT) based on analog sampled-data circuit and singular value decomposition (SVD) algorithm is presented. To begin with, the real and imaginary parts functions of the complex wavelet base are approximated by using SVD algorithm. As the main advantage of this approximation approach is its computational simplicity and general applicability. Next, the complex wavelet circuit is implemented using multiple-loop feedback (MLF) architecture with switched-current (SI) bilinear integrators and current mirrors as basic elements. Finally, the CWT is realized by controlling the clock frequency of the designed SI filters. Simulation results demonstrate the proposed method of implementing the CWT is effective and would be suitable to design other SI circuits as well.

Keywords: Complex wavelet, wavelet transform, analog filters, switched-current circuits, singular value decomposition

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #44, pp. 380-388

Title of the Paper: Design and Analysis of 1MHz Class-E Power Amplifier

Authors: Y. Yusmarnita, Shakir Saat, A. H. Hamidon, Huzaimah Husin, Norezmi Jamal, Kamarudin Kh., Imran Hindustan, Sing Kiong Nguang

Abstract: This paper presents the simulation and experimental of Class-E power amplifier which consists of a load network and a single transistor that is operated as a switch at the carrier frequency of the output signal. Class-E power amplifier is often used in designing a high frequency ac power source because its ability to perform the conversion efficiently even when working at high frequencies with significant reduction in switching losses. In this paper, a 10W Class-E power amplifier is designed, constructed, and tested in the laboratory with operating frequency of 1 MHz. To be specific, SK40C microcontroller board with PIC16F877A is used to generate a pulse width modulation (PWM) switching signal to drive the IRF510 MOSFET. This paper focuses on studying the effect of switching and performance analysis of the Class-E power amplifier behavior at 1MHz frequency. The performance parameter relationship of Class-E power amplifier were observed and analyzed. The theoretical calculations, simulation and experimental results at optimum operation using selected component values are compared and presented. The final result shows an output power is 9.45W with a drain efficiency of 98.44%. It is also shown that both simulation and experimental agree well with theoretical predictions.

Keywords: Class-E power amplifier, zero voltage switching, high frequency power amplifier

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #43, pp. 373-379

Title of the Paper: FPGA-Based Hardware Implementation of Compact AES Encryption Hardware Core

Authors: Atef Ibrahim

Abstract: Most of current embedded applications need AES algorithm implementations of small size and low power consumption to assure safe information conveyance. In this article, we present the implementation of a compact ASE hardware encryption core that is suitable for resource-limited applications based on FPGA technology. The core has 8-bit data path structure and supports encryption with 128-bit keys. The core has been described using VHDL language. The simulation and synthesis results are obtained using ModelSim and Xilinx ISE software tools, respectively. This implementation is compared to the previously reported compact implementations in terms of speed, area, and consumed energy. The implementation results showed that the adopted design achieves significant reduction in area (up to 32.4%) and consumed energy (up to 66.7%). Also, it has a significant increase in speed by ratios ranging from 28.6%to 44.5%. This makes the adopted design more suitable for resource-limited embedded applications.

Keywords: Compact AES hardware implementation, Embedded systems, FPGA, VHDL, Low power hardware design, Hardware security

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #42, pp. 365-372

Title of the Paper: Characterization of Three-Phase Induction Motor Using Conservative Power Theory (CPT)

Authors: Breno Abreu Jr., Flávio A. S. Gonçalves, Helmo K. M. Paredes, F. P. Marafão

Abstract: This paper presents a characterization of three-phase induction motor by means of Conservative Power Theory (CPT). Conservative Power Theory terms are used to determine an equivalent circuit which represents the three-phase induction machine in steady state. The characterized equivalent circuit can be classified in two different types, namely, current source load and voltage source load. In order to validate the approach, a computer simulation of a three-phase induction machine with squirrel cage in several situations of load and voltage feeding were evaluated and compared with the equivalent circuits characterized by CPT terms.

Keywords: Conservative power theory, Three-phase induction machine, Characterization

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #41, pp. 357-364

Title of the Paper: A Novel SEU Self-Test Structure of SRAM-Based Embryonic Electronic Cell

Authors: Li Danyang, Cai Jinyan, Zhu Sai, Meng Yafeng

Abstract: SRAM-based embryonic electronic cell is susceptible to SEU (Single-Event Upset) in radiation space, which severely restricts its application on deep space. Based on the classic cell structure, delay comparison and dual-mode comparison are respectively used in configurable storage module and logic function module to design a novel embryonic electronic cell. The proposed method can effectively detect 1-bit and multi-bit SEUs in both configuration storage module and logic function module in real time. In addition, by using column elimination, the embryonic electronic cell array can achieve real-time self-repair in case of a fault and keep embryonic electronic array system working normally. Results of simulations in a 4-bit ripple carry adder verify the self-test ability of the embryonic electronic cell and self-repair ability of the embryonic electronic cell array.

Keywords: SRAM, embryonic electronic cell, self-test, delay comparison, dual-mode comparison, SEU

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #40, pp. 348-356

Title of the Paper: Adaptive Fault Detection Methods Based on PCA Technique

Authors: Radhia Fazai, Okba Taouali, Nasreddine Bouguila

Abstract: For the improvement of reliability, safety and efficiency advanced methods of supervision, fault detection and fault diagnosis become increasingly important for many technical processes. This holds especially for safety related processes like aircraft, trains, automobiles, power plants and chemical plants. The fault detection based upon multivariate statistical projection method such as Principal Component Analysis (PCA) has attracted more and more interest in academic research and engineering practice. The PCA is an appropriate method for the control of the process based on selection of an optimal number of principal components. In this paper we present the design and a comparative study of offline fault detection indices based on PCA method and adaptive fault detection techniques which used the PCA method. These indices are Squared Prediction Error (SPE), Hotelling’s Statistic (T2), Filtred Squared Prediction Error (Filtred SPE) and i D Index. These indices and the adaptive detection methods are evaluated by handling a numerical example and a Continuous Stirred Tank Reactor (CSTR) benchmark.

Keywords: PCA, SPE, T2, Di , onlie fault detection, PCA conventional, SWPCA, RPCA-FOP

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #39, pp. 338-347

Title of the Paper: Population Density Particle Swarm Optimized Improved Multi-Robot Cooperative Localization Algorithm

Authors: Mengchu Tian, Yuming Bo, Zhimin Chen, Panlong Wu, Cong Yue

Abstract: In light of the accuracy of particle swarm optimization-particle filter (PSO-PF) inadequate for multi-robot cooperative positioning, the paper presents population density particle swarm optimization-particle filter (PDPSO-PF), which draws cooperative co- evolutionary algorithm in ecology into particle swarm optimization. By taking full account of the competitive relationship between the environment and particle swarm, through dynamic adjustment of particle swarm densities based on Lotka-Volterra competition equations, PDPSO-PF improves particle diversities, speeds up the evolution of the algorithm and enhances the effectiveness of prediction for multi-robot positioning. Studies show that PDPSO-PF improves both the convergence speed and accuracy, thus is suitable for multi-robot cooperative positioning.

Keywords: Particle swarm optimization, particle filter, multi-robot, population density, cooperative localization

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #38, pp. 332-337

Title of the Paper: New Processor Array Architecture for DNA Sequence Alignment Using Stevens-Song Algorithm

Authors: Atef Ibrahim, Hamed Elsimary, Abdullah Aljumah, Fayez Gebali

Abstract: This paper proposes a new processor array architecture for an optimized parallel sequence alignment algorithm. This architecture is extracted by applying a nonlinear mapping methodology to the Stevens-Song optimized algorithm after expressing it as Regular Iterative Algorithm (RIA). This methodology uses a data scheduling and node projection techniques to explore the processor array architectures of the algorithm. The proposed architecture is one of the explored architectures and has the advantage that it can be modified to be reused for multiple pass processing in order to increase the number of processing elements that can be packed into a single FPGA and to increase the number of sequences that can be aligned in parallel in a single FPGA. This resolves the potential problem of many FPGA resources left unused for designs that have large values of short read length when using the previously published conventional hardware design. FPGA implementation results show that, for large values of short read lengths (M > 128), the proposed design has a slightly higher speed up and FPGA utilization over the the conventional one.

Keywords: Systolic array, Bioinformatics, Genome sequence alignment, Resequencing applications, Sequencing Technology, Biological computation

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #37, pp. 321-331

Title of the Paper: 99.99% Availability Realization of CATV Networks with Operation Maintenance and Administration Capability

Authors: Xin Wang, Peng Zhang

Abstract: Cable Television (CATV) networks have become the preferred transmission infrastructure to provide integrated high-quality services, and 99.99% availability is the specified ideal target of HFC networks. This paper focuses on the realization of 99.99% availability by operation, administration and maintenance (OAM). In order to ensure the network availability by OAM, the importance of reducing MTTR (Mean Time to Repair) is investigated, and three key influence factors are pointed out, which are the network design structure, the equipment MTBF, and the equipment MTTR. Following which, by comparatively studying three typical network models, the specific measures to improve network availability are developed. The key idea is to select reasonable network structure by combining available operation and maintenance. The numerical results clearly show that these measurements could achieve the availability goal of 99.99%.

Keywords: Network Dependability, Reliability, Availability, Maintainability, MTBF, MTTR

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #36, pp. 313-320

Title of the Paper: Model Predictive Control for Deadbeat Performance of Induction Motor Drives

Authors: Fawzan Salem, Mohamed A. Awadallah, Ehab H. E. Bayoumi

Abstract: The paper presents a design methodology based on model predictive control (MPC) to assure deadbeat performance of both current and speed loops in vector-controlled induction motor drives. Two controllers are independently designed for both loops where the controller parameters are adapted to cope with load changes over a wide range of operation. The performance is compared to that of PI controllers designed based on particle swarm optimization (PSO) and adaptive neuro-fuzzy inference systems (ANFIS). The comparison study shows superior performance of the MPC design.

Keywords: Model predictive control, vector control, induction motor drives, deadbeat performance

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #35, pp. 304-312

Title of the Paper: On The Improvement of the High Frequency Traceability Chain: Application to Attenuators

Authors: Nadia Fezai, Abdessattar Ben Amor

Abstract: The ISO/CEI 17025 standard requires to validate the testing and analytical methods when they are standardized or after amplification or modification of these methods. A measurement uncertainty must also be associated with the results. In High Frequency, All measurement devices must be linked with a reference called standard. In high frequency attenuation, there is no physical standards in this area for most of the national metrology laboratories Thus, a large number of theoretical measurement methods are adopted for the attenuators calibration. This publication describes the feasibility of a computable method HF attenuation made by the laboratory of electrical metrology to ensure traceability to the SI(The international system of units).The method has been completely studied in order to determine its characteristic parameter: attenuation ’A’. All comparative results between classical method and adopted method are presented here.

Keywords: Variable attenuation, Intermediate Frequency (IF), Bolometric bridge, Power sensor, Power variation (PV), Reflection Factor

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #34, pp. 295-303

Title of the Paper: A New Processor Array Structure for Protein Sequence Alignment Using Smith-Waterman Algorithm

Authors: Atef Ibrahim, Hamed Elsimary, Abdullah Aljumah

Abstract: This paper proposes a new processor array structure for the Smith-Waterman with affine gap penalty algorithm to align protein sequences. This architecture is extracted by applying a nonlinear mapping methodology to the Smith-Waterman with affine gap penalty algorithm after expressing it as Regular Iterative Algorithm (RIA). This methodology uses a data scheduling and node projection techniques to explore the processor array structures of the algorithm. The proposed structure is one of the explored structures and has the advantage that it can be modified to enable hardware reuse rather than replicating processing elements of the processor array on a cluster of FPGAs. The proposed hardware structure and the previously reported conventional one are described at the Register Transfer Level (RTL) using VHDL language and implemented using the FPGA technology. The implementation results show that the proposed design has significant higher normalized speed-up (up to 124%) over the conventional design for query sequence lengths less than 512 residues. According to the UniProtKB/Swiss-Prot protein knowledgebase (release 2014 07) statistics, the largest number of sequences (about 80%) have sequence length less than 512 residues that makes the proposed design outperforms the conventional design in terms of speed and area in this sequence lengths range.

Keywords: High performance computing, Parallel processing, Processor arrays, Bio-Computing, Protein sequence alignment, Reconfigurable Computing

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #33, pp. 283-294

Title of the Paper: Prediction and Measurement of Surface Mounted Permanent Magnet Motor Performance with Soft Magnetic Composite and Laminated Steel Stator Cores

Authors: Munaf Salim Najim Al-Din

Abstract: One of the crucial problems associated with high speed electrical machines is the excessive losses, which give rise to the temperature and thus preventing the machine to run at higher speed. In this paper two different stator cores were used with a surface mounted permanent magnet synchronous motor. The first stator core was made from standard laminated steel and the second is made from soft magnetic composite (SMC) material which is formed by surface-insulated iron powder particles. Experimental and computational assessments to the two prototypes were carried out in this paper.

Keywords: Permanent Magnet Motor, Composite and Laminated Steel Stator Cores

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #32, pp. 276-282

Title of the Paper: Research on Two-channel Interleaved Two-stage Paralleled Buck DC-DC Converter for Plasma Cutting Power Supply

Authors: Xi-Jun Yang, Chen Yao, Ning-Yun Zhang, Hao Qu, Hou-Jun Tang, Frede Blaabjerg

Abstract: Buck DC-DC converter is an important and typical power electronic converter with relatively simple topology and rich study contents. Nowadays, it has been widely used as SMPS and high power DC power supplies. As for high power plasma cutting machine, multi-channel interleaved and multi-stage paralleled buck DC-DC converter is the first choice. When designed as a constant DC current supply, it is characteristic of high current precision, good stability and reliability, and it can be designed with current limitation, power equilibrium, constant switching frequency, zero output current steady-state error and phase shift driving. In the paper, a two-channel interleaved, two-stage paralleled buck DC-DC converter is analyzed and designed by using sliding mode control (SMC) and simulated by means of MATLAB/SIMULINK. The basic principle of sliding mode control is also reviewed. Then the experimental setup of plasma cutting machine (PCM) DC current supply is implemented on the basis of the theoretical analysis, which outputs the rated current of 260A and the rated DC voltage of 150V, and the switching frequency is selected as 10kHz. The gained results prove the designed sliding mode control.

Keywords: Plasma cutting power supply, buck DC-DC converter, Two-channel interleaved, Two-stage paralleled, Sliding mode control, Current limitation, Constant switching frequency, Output voltage steady-state error, Phase shift driving

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #31, pp. 262-275

Title of the Paper: Research and Design of Coupled Magnetic Resonant Power Transfer System

Authors: Shuai Zhong, Chen Yao, Hou-Jun Tang, Kai-Xiong Ma

Abstract: Coupled Magnetic Resonant Power Transfer (MRCPT) Technology is a kind of Wireless Power Transfer (WPT) technology which is flexible in space and has the advantage of transmission distance. It is suitable for the industrial and civil use in the future. In this paper a model of coupled magnetic resonant power transfer system is established and the features of the system is analyzed and a device based on E-Class amplifier is designed to verify the theoretical analysis. The results of this paper could provide a useful reference to design wireless power transfer system.

Keywords: Wireless power transfer, Coupled magnetic resonant, Class-E amplifier, Modeling, Electromagnetics, Mutual inductance, High frequency converter

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #30, pp. 253-261

Title of the Paper: Research on Meander-Type Coupled Structure of Capacitively Coupled Power Transfer System

Authors: Shiyun Xie, Yugang Su, Chunsen Tang, Long Chen

Abstract: Capacitively coupled power transfer(CCPT)system is an alternative solution to tranditional inductive power transfer (IPT) system in certain high Electromagnetic compatibility applications with the advantages of being able to transfer power across metal barriers and having low standing power losses. Aiming at the problem of low transporting capacity and efficiency of typical CCPT system based flat elcctrodes in the loosely coupled mode, a new meander-type laminated coupled structrue was proposed in this paper. The equivalent circuit model of the new meander-type laminated structure was established, and the simulation analysis results showed that output power of the system with the new structure is two times higher than that of the traditional type. Finally, the experiment results verified the availability of the new structure and the theory analysis method.

Keywords: Capacitively coupled power transfer(CCPT), meander-type, laminated coupled, efficiency

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #29, pp. 247-252

Title of the Paper: A New Audio Bio-Feedback System for Postural Stability Enhancement

Authors: Giovanni Costantini, Daniele Casali, Massimiliano Todisco, Giovanni Maccioni, Daniele Giansanti

Abstract: In this paper, we describe a bio-feedback system for rehabilitation based on an accelerometric sensor, a processing unit and an output unit. The sensory unit, which incorporates a cell with three uni-axial accelerometers and three rate gyroscopes, is mounted on the subject’s back (L5 level) using a velcro belt and allows to evaluate the trunk accelerations in the anterior-posterior (AP) and medial-lateral (ML) directions. The processing unit is composed by a laptop with Arduino board, able to acquire in real time data coming from sensory unit through the data acquisition module of Max/MSP, and to produce an audio output. The output unit is a pair of headphones which produce a kind of sound whose activation level is proportional to the magnitude of patient’s displacement. A set of experiments have been carried out in order to measure the performance of this system, and results show that it can significantly improve rehabilitation times.

Keywords: Bio-feedback, postural stability, sensor interface, audio feedback, e-rehabilitation

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #28, pp. 237-246

Title of the Paper: Global State-Feedback Stabilization for a Class of Uncertain Nonholonomic Systems with Partial Inputs Saturation

Authors: Fangzheng Gao, Yanling Shang

Abstract: This paper investigates the problem of global stabilization by state feedback for a class of uncertain nonholonomic systems in chained form with partial inputs saturation. By using input-state-scaling technique and backstepping recursive approach, a state feedback control strategy is presented. With the help of a switching control strategy, the designed controller renders that the states of closed-loop system are globally asymptotically regulated to zero. A simulation example is provided to illustrate the effectiveness of the proposed approach.

Keywords: Nonholonomic systems, Partial inputs saturation, Backstepping, State feedback, Global stabilization

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #27, pp. 230-236

Title of the Paper: Analysis and Design of Wireless Power Transfer: A Capacitive Based Method for Low Power Applications

Authors: Kamarudin Kh., Shakir Saat, Y. Yusmarnita, Norezmi Jamal

Abstract: This report presents an analysis and design of a Capacitive Power Transfer (CPT) system. CPT is a new wireless energy transfer technology, which employ electrical field to transfer electrical energy without wires. This CPT method is chosen in this project because of its capability of being able to transfer power across metal barriers and also has the potential to reduce electromagnetic interference (EMI). The CPT system that has been designed uses a class E converter. A class E converter is based on the hypothesis that the active device is operated as a switch, which is different from the usual current source mode, regardless of whether a voltage (FET) or current (BJT) controlled device is adopted. One of the advantages of a class E converter is its ability to produce zero voltage switching (ZVS) which is guaranteed in this work to yield a high efficiency CPT system. Finally, a prototype of a CPT system was successfully developed which was capable to transmit 2mW of power at 4MHz frequency, with 90.7% efficiency, through a plate of size 12cm x 12cm with thickness of 0.1cm.

Keywords: Capacitive Power Transfer (CPT), Class E MOSFET Converter, Zero Voltage Switching

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #26, pp. 221-229

Title of the Paper: 3.67GHz High-Linearity Low Noise Amplifier with Simple Topology

Authors: Yinhua Yao, Tongxiu Fan

Abstract: This paper describes the design, implementation, and test of a 3.67GHz low noise amplifier (LNA) for intermediate frequency amplifier using pseudomorphic high electron mobility transistor (pHEMT). The LNA circuit is optimized and simulated using Advanced Designed System (ADS). The layout of the amplifier is processed using Protel 99SE. The simulation results show that the gain and noise figure (NF) are 13.535dB and 1.47dB with an output 3rd order intercept point (OIP3) of 37.441dBm, while input and output voltage standing wave ratios(VSWRs) are 1.539 and 1.394, respectively. The tendencies of measured gain, NF, and VSWRs are in a good agreement with those of simulated ones. The fabricated LNA, with a degraded NF below 1.718dB, achieves 13.16dB gain similar to the simulated result. The LNA provides higher than simulations but reasonably acceptable input and output VSWRs of 1.539 and 1.710. The measured OIP3 and output 1dB compression point are better than 33.25dBm and 19.4dBm, respectively.

Keywords: low noise amplifier, impedance matching, linearity

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #25, pp. 216-220

Title of the Paper: Run-time Fallback and Multiboot Technique for Embedded Platform Using Low-Cost Spartan-6 FPGA

Authors: Ahmed Hanafi, Mohammed Karim

Abstract: This paper aims at demonstrating the whole process allowing implementing a robust in-system update solution for Microblaze-based embedded systems using low-cost and low-power consuming Spartan-6 FPGA. In this work, we design a run-time full reconfigurable embedded platform based on the Spartan-6 Multiboot and fallback features. The FPGA Multiboot feature enables switching between two or more con-figuration files, on the fly (during normal operation), from an external SPI Flash memory. When an error or an interruption is detected during the Multiboot configuration process, the FPGA triggers fallback feature that ensures the configuration with a golden “safe” image. Embedded development kit (EDK) prepared by Xilinx company is employed to implement the embedded platform on a Spartan-6 evaluation board (i.e., SP605). Based on the Internal Configuration Access Port (ICAP) primitive in the FPGA fabric, we used Xilinx LogiCORE IP AXI HWICAP (Advanced eXtensible Interface Hardware ICAP) core to write software programs that modify the circuit structure and functionality during run-time. This IP Core has been originally designed to support the Run-time Partial Reconfiguration (PR) feature for the Virtex-4, Virtex-5, Virtex-6 family FPGA. Xilinx added support for Spartan-6 family FPGA in 2010 and we decide to use it to facilitate the run-time full reconfiguration process.

Keywords: Run-time full reconfiguration, Multiboot, Fallback, ICAP, Microblaze, AXI HWICAP, FPGA

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #24, pp. 208-215

Title of the Paper: Multi-Agent Based Protection System for Distribution System with DG

Authors: Jin Shagn, Nengling Tai, Qi Liu

Abstract: This paper introduces the basic structure of multi-agent based protection system for distribution system with DGs. The entire system consists of intelligent agents and communication system. Intelligent agents can be divided into three layers, the bottom layer, the middle layer and the upper layer. The design of the agent in different layer is analyzed in detail. Communication system is the bridge of multi-agent system (MAS). The transmission mode, selective communication and other principles are discussed to improve the transmission efficiency. Finally, some evaluations are proposed, which provides the design of MAS with reference.

Keywords: multi-agent, protection, distribution system, DG, communication

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #23, pp. 202-207

Title of the Paper: Design of Class-D Audio Power Amplifiers in 130 nm SOI-BCD Technology for Automotive Applications

Authors: Karim El Khadiri, Hassan Qjidaa

Abstract: In this work, design of class D audio power amplifier output stage implemented in 130 nm Silicon-on-Insulator (SOI) technology is proposed for high power efficiency and low distortion. The class-D audio amplifier consists of two DMOS power transistors in a totem-pole configuration, a gate driver, a shunt regulator, a ramp generator, a comparator and an integrator. The design method proposed in this study uses two on-chip shunt regulators to provide stable on-chip supply voltages to the gate driver circuits and a second-order feedback loop to suppress supply ripple. Its performance was found to be better than previously published output stages implemented in SOI based BCD processes, which are typically more complex and costly. The proposed class-D audio amplifier was designed, simulated and layed out in Cadence using TSMC 130 nm SOI-BCD technology. The class-D audio amplifier achieves a total root-mean-square (RMS) output power of 0.5W, a total harmonic distortion plus noise (THD+N) at the 8-Ω load less than 0.06%, and a power efficiency of 93%. The final design occupies approximately 1.5mm2.

Keywords: Class-D Amplifier, Output stage, SOI technology, Triangle-wave generator, Pulse-width-modulation

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #22, pp. 193-201

Title of the Paper: FPGA Coprocessor-Based IMM-SDCMKF Application to a Radar Maneuvering Target Tracking System

Authors: Bao-Bao Wang, Quan-sheng Wang, Lian-zhong Zhang

Abstract: This paper presents a maneuvering target tracking system using Interacted Multiple Model-Second Debiased Converted Measurement Kalman Filter (IMM-SDCMKF) based on FPGA coprocessor. IMM-SDCMKF is considered one of the most effective algorithms for maneuvering target tracking. However, the computation of this algorithm is time-cost and complex. The traditional design approach is unable to meet the high-speed real-time signal processing needs. In this tracking system, the FPGA is used as a coprocessor of the DSP, and the large amount of calculation of IMM-SDCMKF algorithm is realized in FPGA. DSP is in charge of the scheduling of the total tracking algorithm and the control of the data stream, which resolves the problem of the concurrency and real time in the realization of the single DSP scheme. The designed tracking system ensures the accuracy of the data processing as well. The experiment results show that the designed scheme meets the high precision and real time of the maneuvering target tracking system.

Keywords: Maneuvering target tracking, IMM-SDCMKF, FPGA, Coprocessor, Real-time

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #21, pp. 183-192

Title of the Paper: Metaheuristic Techniques for the Analog Circuits Performances Optimization -A Comparison Issue-

Authors: Bachir Benhala

Abstract: Particle Swarm Optimization (PSO), Ant Colony Optimization (ACO), Genetic Algorithm (GA) and Simulated Annealing (SA) are mostly used as metaheuristic for electronic circuit’s performances optimization. Despite their different research techniques, these methods achieve the optimal solution for analog circuit design. The aim of this paper is to make a comparison between the performances reached by those four techniques in the optimal sizing of a CMOS second generation current conveyor (CCII) and an operational amplifier (Op-Amp). The highlighted results obtained by the used algorithms, will be compared in terms of optimum quality, convergence rate and the computing time.

Keywords: Swarm Intelligence, Evolutionary Algorithm, Simulated Annealing, Second Generation Current Conveyor, Operational Amplifier

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #20, pp. 174-182

Title of the Paper: A Novel Embryonics System with Evolutionary Ability

Authors: Sai Zhu, Jinyan Cai, Yafeng Meng

Abstract: Based on an analysis of the advantages and disadvantages of row/column elimination and cell elimination repair methods in embryonics (embryological electronics, embryonics), we developed a novel embryonics hardware structure with evolutionary ability and a corresponding self-repair method. The proposed embryonics system has a function layer, a repair layer and an evolution layer. Target circuit function is implemented through the function layer, column elimination self-repair is implemented by the repair layer, and the evolution layer can be used to initiate evolution of the circuit operating on the function layer. Importantly, the proposed self-repair method has evolution property. Depending on changes in self-repair capacity, two repair modes can be used: elimination self-repair and evolution self-repair. The faulty circuit can be repaired online in real-time through the elimination self-repair mode, and the evolution self-repair mode can fully utilize the redundancy resources through evolution of the circuit form. By combining these two modes, the embryonics system and self-repair methods presented here ensure that the circuit realized on the hardware can not only be repaired in real time, but also that utilization of embryonics and the circuit self-repair capacity are improved.

Keywords: embryonics, self-repair capacity, evolutionary ability, elimination repair mode, evolution repair mode

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #19, pp. 164-173

Title of the Paper: The DC Behavioural Electrothermal Model of Silicon Carbide Power MOSFETs under SPICE

Authors: A. Lakrim, D. Tahri

Abstract: This paper presents a new behavioural electrothermal model of power Silicon Carbide (SiC) MOSFET under SPICE. This model is based on the MOS model level 1of SPICE, in which phenomena such as Drain Leakage Current IDSS, On-State Resistance RDSon, gate Threshold voltage VGSth, the transconductance (gfs), I-V Characteristics Body diode, temperature-dependent and self-heating are included and represented using behavioural blocks ABM (Analog Behavioural Models) of Spice library. This ultimately makes this model flexible and easily can be integrated into the various Spice -based simulation softwares. The internal junction temperature of the component is calculated on the basis of the thermal model through the electric power dissipated inside and its thermal impedance in the form of the localized Foster canonical network. The model parameters are extracted from manufacturers' data (curves data sheets) using polynomial interpolation with the method of simulated annealing (SA) and weighted least squares (WLS). This model takes into account the various important phenomena within transistor. The effectiveness of the presented model has been verified by Spice simulation results and as well as by data measurement for SiC MOS transistor C2M0025120D CREE (1200V, 90A).

Keywords: SiC power MOSFET, DC Electro-thermal Model, ABM Spice library, SPICE Behavioural Modeling, C2M0025120D CREE

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #18, pp. 157-163

Title of the Paper: Simulation and Analysis of Electromagnetic Transient Characteristics of Controllable Reactor of Transformer Type

Authors: Tian Mingxing, Zhao Qianru, Yin Jianning, Liu Yibin

Abstract: This paper analyzed the winding construction of Controllable Reactor of Transformer Type (CRT), based on the duality theory a new transient model of CRT is proposed. It can reflect the electric circuit coupled with magnetic circuit correctly. Fitting the magnetization curve with the function fitting method and the simulation results prove the accuracy of the model. Proposing divide CRT’s working process into operating process and grade-changing process. And analyze and research the transient processes of the two processes respectively. According to the transient model build CRT no-load switching-in mathematical model, do simulation research with ATP-EMTP, analyze the phenomena of magnetizing inrush current in operating process. And analyze current of each winding in grade-changing process, the simulation results verify the correctness of the model and analyze the transient characteristic of CRT.

Keywords: Controllable Reactor of Transformer Type, Transient model, ATP-EMTP, Magnetizing inrush current, Transient characteristic

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #17, pp. 151-156

Title of the Paper: Stabilization of Differential Linear Repetitive Processes Saturated Systems by State Feedback Control

Authors: Said Kririm, Abdelaziz Hmamed

Abstract: The stabilization of linear differential linear repetitive processes subject to saturating controls is addressed. Sufficient conditions obtained via a linear matrix inequality (LMI) formulation are stated to guarantee both the local stabilization and the satisfaction of some performance requirements. The method of synthesis consists in determining simultaneously a state feedback control law and an associated domain of safe admissible states for which the stability of the closed-loop system is guaranteed. Two cases are considered: the first one, the control may saturate and limits may be attained. The second one, the control does not saturate and limits are avoided.

Keywords: Differential linear repetitive processes, State-feedback control, Lyapunov functions, Saturation, LMIs

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #16, pp. 142-150

Title of the Paper: Hexapod Type Microrobot Controlled by Power Type IC of Artificial Neural Networks

Authors: Kei Iwata, Yuki Okane, Yohei Asano, Yuki Ishihara, Kazuki Sugita, Satohiro Chiba, Satoko Ono, Minami Takato, Ken Saito, Fumio Uchikoba

Abstract: In this paper, we report the hexapod type micro robot controlled by the neural networks. MEMS (Micro Electro Mechanical System) technology that based on the semiconductor process is used for fabrication of the microrobot. The rotational actuator is composed of four artificial muscle wires that is family of SMA (shape memory alloy). The power type bare chip IC is used for neural networks control systems of the microrobot. The IC includes 4 cell body models, 12 inhibitory synaptic models and current mirror circuits. This power type IC bare chip can output the CPG (Central Pattern Generator) waveform required for walking of the microrobot. By using power type bare chip IC, fine tuning of output current is achieved and the additional amplifier circuit is eliminated. As the result, we indicate possibility of downsizing of driving circuit and the stable actuator control. The sideways, endways, and height dimensions of the microrobot are 4.0mm, 2.7mm, and 2.5mm, respectively. The walking speed is 15mm / min and the step width is 0.6mm.

Keywords: Microrobot, Neural networks, IC bare chip, MEMS technology, Hexapod type, Artificial muscle wire

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #15, pp. 134-141

Title of the Paper: Analysis of DAR IMPATT Diode for Some Frequency Bands

Authors: Alexander Zemliak, Fernando Reyes, Jaime Cid, Sergio Vergara, Evgeniy Machusskiy

Abstract: The analysis of DAR IMPATT diodes has been realized on basis of the precise drift-diffusion nonlinear model. The admittance characteristics of the DAR diode were analyzed in very wide frequency band from 30 up to 360 GHz. The energy characteristics have been optimized for the second high frequency band near the 220 GHz.

Keywords: Active layer structure analysis, DAR IMPATT diode, high frequency band, implicit numerical scheme

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #14, pp. 128-133

Title of the Paper: Design of 33-40GHz Low Power VCO in 90-nm CMOS Technology

Authors: Zhu Li, Zhigong Wang, Zhiqun Li, Qin Li

Abstract: This paper presents the IC design of a low power, wide tuning range and low phase noise voltage-controlled oscillator (VCO) in a standard 90-nm CMOS technology. The newly proposed current-reuse cross-connected pair is utilized as a negative conductance generator to compensate the energy loss of the resonator. The supply current is reduced by half compared to that of the conventional LC-VCO. An LC tank with switched capacitor is used to extend the overall VCO tuning range. The VCO achieves a tuning range of 33~40.4 GHz exhibiting a frequency tuning range (FTR) of 20.2%, a phase noise of -103.4 dBc/Hz at 1-MHz offset from 36-GHz carrier and showed an excellent FOM of –189dB. With the voltage supply of 1.5 V, the core circuit of VCO draws only 1.9mA DC current. The VCO is fully differential and integrated in a PLL circuit in the 90-nm CMOS technology.

Keywords: CMOS, Microwave, millimeter wave, Switched capacitor, Phase noise, VCO

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #13, pp. 118-127

Title of the Paper: Low Power Heterogeneous Adder

Authors: Karthick S, Valarmathy S, Prabhu E

Abstract: Flexibility and Portability has increased the requirement of Low Power components in fields like multimedia, signal processing and other computing applications. Adders are the essential computing elements in such applications. However the present adder architectures with hybrid/heterogeneous features provide performance variations but limits to consume less power. In this paper, low power heterogeneous adder architecture is proposed to enable flexibility to the computing applications and consume less power. 128 bit heterogeneous adder architecture is built using three low power sub-adders (ripple carry, carry look ahead and carry bypass adders). Adder variants in sub-adders block of heterogeneous adder architecture enables to select required quality metrics viz., area, timing and power, for the design. Application requirements like low power – same performance, low power – low area, variable performance can be selected. Designs are demonstrated using Verilog HDL by synthesizing with Cadence’s RTL Compiler and mapped to TSMC 65nm technological library node.

Keywords: Heterogeneous adder, Power delay trade-off, Low Power VLSI, Digital Filter, Verilog

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #12, pp. 109-117

Title of the Paper: Design of a LNA in The Frequency Band 1.8-2.2ghz in CMOS Technology

Authors: Xiaorong Zhao, Honghui Fan, Feiyue Ye , Sheng He, Haijun Huang

Abstract: As the first active stage of receivers, Low Noise Amplifier (LNA) play a critical role in the overall performance and their design is governed by the parameters. This paper presents the design of LNA and development of low bias (VDS=3V,ID=20mA), which operating in frequency range 1.8-2.2GHz using a feedback circuit. The proposed Single Stage and Two Stage LNA are simulated with Advanced Design System (ADS) 2012. The paper compares the simulated results of Single Stage LNA and Two Stage LNA. Simulation results of the final Single Stage LNA have indicated that the S21=16.332±0.348dB, NF=0.445±0.05dB, S12<-22.441dB and S11<-16.631dB over the wide frequency band of 1.8-2.2GHz. Simulation results of the final Two Stage LNA have indicated that the S21=29.929±0.591dB, NF=0.482±0.055dB, S12<-40.783dB and S11<-16.126dB over the wide frequency band of 1.8-2.2GHz.

Keywords: Low noise amplifier, HEMT, Feedback, Noise Figure, ADS, RF

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #11, pp. 100-108

Title of the Paper: Study of Harmonics Generated in Rectifier Substation of Railway System

Authors: Márcio Zamboti Fortes, Fabricio Da Silva Macedo, Pablo Mourente Miguel, Vitor Hugo Ferreira

Abstract: The rectifiers that feed electric trains can cause undesirable effects on substation feeding systems, as to increase electrical losses, equipment malfunction and harmonic overvoltage. This research analysis a real case at railway substation and uses a tool in the ATP software (Alternative Transients Program), with the presentation of the results obtained by simulations and the analysis of these results with proposals for solutions, supporting electric engineering maintenance work teams.

Keywords: Maintenance, Software For Engineering Applications, Software Simulation, Harmonics, Railway Systems

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #10, pp. 89-99

Title of the Paper: Synthesis of Adder Circuit Using Cartesian Genetic Programming

Authors: S. Asha, R. Rani Hemamalini

Abstract: Digital adders form a significant part of the arithmetic unit in the processors. Many Digital Signal Processing (DSP) algorithms equally uses adder and multiplier element as its component to achieve the required arithmetic operation. Hence it is important to optimize the adder circuit in the gate-level itself to design it for the required standards. Recently there are various bio-inspired optimization algorithms which efficiently synthesize digital circuits like adders and multipliers. Optimization algorithms like genetic Algorithm (GA), Particle swarm optimization (PSO) and Harmony Search (HS) has proved its efficiency in various optimization problems. We utilize the conventional Cartesian genetic programming (CGP) along with the shuffling mechanism to evolve the 4X4 adder circuit using only two input NAND gate library. The evolved adder circuit is compared with the existing adder circuits to prove its performance benefits. This evolved 4-bit adder is used further to synthesis higher order adders for its real time performance benefits.

Keywords: Evolved adder, Cartesian Genetic Programming, Partitioned Multiplier, Bio-Inspired Computation, Genetic Algorithm, Optimization of Digital circuits

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #9, pp. 83-88

Title of the Paper: Frequency Correction Method of OCXO and its Application in the Data Acquisition of Electrical Prospecting

Authors: Shao-Heng Chun, Ru-Jun Chen, Bi-Wen Xiang

Abstract: The GPS (Global Position System) timing is vulnerable to the external environment which makes the synchronous timing become unlocked easily. Based on FPGA (Field Programmable Gate Array), this paper aims to design a high precision synchronous timing by GPS disciplined oven controlled crystal oscillator (OCXO). The application of building a delay line inside FPGA to measure the time interval with resolution as 71ps and 10ps, ensuring the high accuracy of timing. The average filter is employed to suppress the random noise brought by PPS (Pulses per Second) which is used as a standard signal to correct the frequency of the OCXO, which is demonstrated to be very effective. The synchronous timing is realized simultaneously with the discipline of OCXO, which guarantees the high initial precision between LPS (Local Pulses per Second) and PPS whenever the GPS becomes unlocked. After frequency correction is completed, the timing error reaches 410 ns, 1.6 us, 2.0 us and 33.0 us after the GPS receiver is unlocked by 150 min, 6 h, 12 h, and 24 h respectively, which is more accurate than a commercial product V5-2000. Long-term measurement of timing error demonstrates that the method proposed by us can combine the advantages of GPS timing and OCXO timing, thus to solve the problem existed in the GPS timing. It not only meets the precision requirements of synchronous timing in all the distributed acquisition systems for electrical prospecting, but also can be applied in other industrial fields need high precision timing. The design is realized in one FPGA chip, which greatly reduces the quantities of peripheral elements and simplifies the complexity of the peripheral circuit, thus reduces the cost and power.

Keywords: GPS timing, OCXO, frequency calibration, synchronization, FPGA, electrical prospecting

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #8, pp. 68-82

Title of the Paper: Single-Ended and Fully-Differential Current-Input Current-Output Universal Frequency Filter with Transconductace and Transresistance Amplifiers

Authors: L. Langhammer, J. Jerabek, J. Polak, P. Cika

Abstract: A new filtering structure of the 2nd-order universal frequency filter is presented. The proposed filter operates in a current-input current-output form and it is designed using signal-flow graphs (SFG) method. Operational transconductance amplifiers (OTAs), current follower (CF) and operational transresistance amplifier (OTRA) are used in the proposal. The filter possesses ability to adjust the pole frequency and quality factor of the filter without violating each other. All output responses are taken directly from high-impedance outputs of used active elements. The proposal requires only two external passive elements, namely two capacitors which are both grounded. The proposed filter has been also designed in its fully-differential form. The proper function of the proposed S-E and F-D filter is verified by PSpice simulations and in case of the S-E filter also by experimental measurements. Demonstrations of possibility to tune the pole frequency and quality factor of the proposed S-E and F-D filter are illustrated in the paper. Subsequently, comparison of simulations of S-E and F-D structures of the proposed filter and comparison of results of the S-E filter obtained from simulations and experimental measurements are also included.

Keywords: Frequency filter, Transconductance amplifier, Transresistance amplifier, Simulation, Experimental measurement

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #7, pp. 56-67

Title of the Paper: Cuk Converter Fed Adjustable Speed DC Motor Driven Electrical Single Stage Centrifugal Pump

Authors: Saswati Swapna Dash, Byamakesh Nayak

Abstract: This paper presents a Robust Control of Cuk Converter Fed DC motor drive connected to an electrical single stage centrifugal Pump for small scale irrigation. Cuk converter can be used for both voltage buck and boost mode with polarity reversal. In this paper the transient modeling of Cuk converter with motor load and electrical single stage centrifugal pump is carried out. The averaging is done by state-space average analysis followed by small signal model analysis for linearization. The compensators for closed loop control are designed by classical control technique. The experiment is done in MATLAB work environment and the result is verified by Simulation.

Keywords: Cuk converter, Current mode control, separately excited DC motor, state-space average analysis, electrical single stage (ESS) centrifugal pump, small signal analysis, robust control, small scale irrigation

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #6, pp. 46-55

Title of the Paper: Multi-Layer System-on-Substrate for Ka-Band Foreign Object Debris (FOD) Detection Sensor

Authors: Ghulam Mehdi, Jungang Miao

Abstract: Presence of Foreign object debris (FOD) at airport runways is an immense threat to flight safety. Such objects may cause potential damage to the aircraft especially during the take off and landing. This paper introduces the design of a low-cost Ka-band FOD radar sensor adopting state-of-the-art system-on-substrate (SoS) approach. Contrary to the reported single-layer SoS design approach, multi-layer SoS configuration is introduced. The frequency modulated continuous-wave (FMCW) front-end transceiver and the integrated transmit and receive antennas are realized in multi-layer configuration. The front-end transceiver is mainly designed employing substrate integrated waveguide (SIW) circuits on low-cost 12 mil thick R4003C substrate. The front-end transceiver comprises of MMICs and passive structures such as SIW band-pass filters, SIW Wilkinson power divider and SIW-to-microstrip transitions. The antenna is of SIW traveling-wave slot array (TWSA) type realized on 60 mil thick R4003C. Unlike conventional coaxial matched loads used in SIW-TWSA, a virtually grounded resistive matched load is introduced for termination of such antenna in SIW technology. The simulation results of the proposed antenna and transceiver front-end are presented.

Keywords: Foreign object debris, system-on-substrate, substrate integrated waveguide, frequency modulated continuous-wave, slot array antenna

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #5, pp. 31-45

Title of the Paper: Three-Dimensional Devices Transport Simulation Lifetime and Relaxation Semiconductor

Authors: S. F. Nouar, S. Mansouri, M. Amrani, P. Marie, A. Massoum

Abstract: Our objectif consists in creating a 3D three-dimensional simulator conceived for the study of components with low geometry of conception, allows determining in the volume of a structure, the distributions of potential and the densities of free carries according to a given polarization, by resolution of Poisson ‘s equation as well as both equations of continuity. The initial version can simulate components based on lifetime semiconductor. Our work consists in making a comparison between lifetime and relaxation semiconductors in the conduction mode, with the aim of creating a more developed simulator. We consider the case corresponding to two values very different from diffusion lifetime τ0 which is a measure of the life expectancy in diet of transport, corresponding to two different semiconductor, lifetime and relaxationSC. The method of resolution consists of a linearization of the equations of transport by the method of a finite-difference. The algorithm adapted to the resolution of the not linear equations and strongly coupled ensuing from the physical model is the one of Newton Raphson, However to allow better one convergence and consequently an improvement in the weather of 3D calculation often prohibitive, a combined method, integrating at the same time the algorithm of Newton and that of Gummel was finalized. The tests of simulation for the validation of the model are made on the long diodes of type PIN.

Keywords: Lifetime semiconductor, relaxation semiconductor, three-dimensional Simulation, Newton algorithm, Gummel algorithm

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #4, pp. 24-30

Title of the Paper: Response of GaAs Photovoltaic Converters Under Pulsed Laser Illumination

Authors: Tiqiang Shan, Xinglin Qi

Abstract: GaAs photovoltaic converters are useful for the conversion of monochromatic light into electrical power in numerous military and industrial applications. In these applications, high output voltages are often demanded. One approach can be used to match the required voltage requirements is single GaAs photovoltaic converter plus DC-DC converter. However, DC-DC converter runs on pulsed electrical energy naturally. Pulsed operation of photovoltaic converter has significant differences from operation under continuous illumination. Many issues must be addressed before high efficiency transmission of power by pulsed laser can be achieved in practical applications. In an effort to understand these issues, a series of studies are undertaken in this paper. The response of GaAs photovoltaic converter to monochromatic pulsed illumination at high intensity is modeled theoretically. As the simulation results showed, the conversion efficiency of GaAs photovoltaic converter to pulsed laser light is dependent on the converter minority carrier lifetime, the width and frequency of the pulses, and the incident power. In addition, three main circuit effects which decrease the efficiency of GaAs photovoltaic converter for pulsed illumination are discussed detailedly. Finally, some feasible approaches are proposed to solve these issues.

Keywords: GaAs photovoltaic converter, pulsed laser, minority carrier lifetime, circuit effects, DC-DC converter

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #3, pp. 19-23

Title of the Paper: A New Trans-Admittance Mode Biquad Filter Using MO-VDTA

Authors: Chandra Shankar, Sajai Vir Singh

Abstract: In this paper, a new trans-admittance-mode biquad filter configuration based on two multi output voltage differencing transconductance amplifiers (MO-VDTAs) as newly active elements is proposed which also consists of two grounded MOS resistors and two capacitors with one of the capacitor is being permanently grounded. The proposed configuration is competent of realizing trans-admittance-mode low pass (LP), band pass (BP), high pass (HP), band reject (BR) and all pass (AP) filtering responses. Moreover, the proposed circuit offers several excellent features such as electronic tunability of pole frequency and quality factor, low active and passive sensitivity and low power consumption. To justify the theoretical analysis, the proposed circuit is simulated using PSPICE in 0.35μm CMOS technology from TSMC.

Keywords: VDTA, TAM, Biquad, Filter, Analog signal processing, Tunable

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #2, pp. 8-18

Title of the Paper: Transient Analysis of Track Circuit Based on Finite Differential Method

Authors: You-Peng Zhang, Lei Wei

Abstract: In allusion to the research on track circuit are mostly focused on spatial domain at present, the finite differential method is put forward to the time domain analysis of track circuit in this paper, in the theory of partial differential equation numerical solution. A new differential formation of track circuit based on Lax format is established and according to the lumped parameter equivalent circuit, the boundary conditions at the beginning and terminal are confirmed. Through example, the time domain solution conform to the transmission characteristic of track circuits, and the accuracy of the method is validated by comparing the simulation result with that of ADIFDTD method. Therefore, the finite differential method can be used to transient analysis of track circuit.

Keywords: Finite Differential Method, Lumped Parameter Equivalent Circuit, Track Circuit, Time Domain Solution, Transient Analysis, ADI-FDTD

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 14, 2015, Art. #1, pp. 1-7